1. Field of the Invention
The present invention relates to manufacture of electrical circuitry and more particularly concerns manufacture of electrical circuitry incorporating an elevated interconnection feature having a three dimensional configuration including a contact that extends from the plane of the circuit.
2. Description of Related Art
Both flexible and rigid printed circuits are connected to similar circuits and other components by means of various types of connecting devices. Flat, flexible printed circuit connecting cables warrant use of similarly configured connecting devices and have been developed to a point where connection between one such printed circuit cable and another is made by providing a plurality of projecting metallic interconnection features that may be pressed against either similar features or mating metallic connecting pads on the other circuit component or components. Flexible circuit terminations or connecting wafers of this type are described in U.S. Pat. No. 4,125,310 to Patrick A. Reardon, II, U.S. Pat. No. 4,116,517 to Selvin, et al, and U.S. Pat. No. 4,453,795 to Moulin, et al. The connectors of these patents embody a substrate having traces chemically milled thereon with a plurality of metallic raised features later formed to project from the plane of the circuit conductors. Thus, when two such connectors are placed face to face with the raised features of one in registration and contact with the other, the planes of the etched electrical circuits are suitably spaced from one another because of the projection features. The two circuits may be physically clamped together to press the features against one another, thereby making firm electrical contact between the two circuits. These terminations are effective and reliable in operation but difficult, costly and time consuming to manufacture. Major problems in manufacture of such connectors derive from the fact that the projecting contact buttons must be fabricated separately from (either after or before) the fabrication of the circuitry itself. This creates difficult registration problems between the circuit, the areas where the holes are to be drilled and contact buttons to be placed and the circuit art work (optical mask) that may need to be positioned on either side of the dielectric core.
Where raised interconnection features are employed, as in flexible circuit termination wafers, it is necessary also to plate projecting contact features on pads formed in the circuitry which has been previously etched. These features must be precisely registered with the selected pads and with the datum of the panel. However, the panels have been previously processed to form the circuit traces so that further stresses occurring in such processing effect changes in dimension which cause severe registration problems.
In some cases the projecting interconnection features or dots may be formed first, before the remainder of the etched circuit is formed, but in any event the feature must be formed separately at a different time than the time of forming the etched circuitry, and thus registration problems are magnified.
Conventional etched circuit processes in general have a number of disadvantages. Dimensional precision is difficult to achieve. The use of various etching, stripping and cleaning fluids requires special handling of hazardous chemicals. Techniques for disposal of the resulting effluents are complex, expensive and subject to strict government controls. Etched circuit processing has a relatively low yield, greatly increasing the cost of the processing, which inherently involves a large number of costly processing steps.
In a co-pending application, Ser. No. 580,758, filed Sep. 11, 1990, of William R. Crumly, Christopher M. Schreiber and Haim Feigenbaum, for Three Dimensional Electroformed Circuitry, assigned to the assignee of the present application, there is described a method of forming elevated contact features by electroforming or additive processes which avoid and substantially eliminate sequential etching and plating processes.
In the processes of the prior application for Three Dimensional Electroformed Circuitry, an electrically conductive mandrel, having three dimensional features formed thereon, is electroplated in a selected pattern to additively form the circuitry together with its three dimensional contact and interconnection features directly therein. This process requires a specially formed and prepared mandrel which introduces additional steps and complexity into the process.
Accordingly, it is an object of the present invention to provide methods and apparatus for manufacture of electrical three dimensional circuitry which avoid or minimize above mentioned problems and which eliminate sequential etching and plating processes employed in the formation of three dimensional circuitry.